A Fast Parallel Squarer Based on Divide and Conquer

Fast and small squarers are needed in many applications such as image compression A new family of high performance parallel squarers based on the divide and conquer method is reported Our main result was realizing the basis cases of the divide and conquer recursion by using optimized n bit primitive squarers where n is in the range of to This method reduced the gate count and provided shorter critical paths A chip implementing an bit squarer was designed fabricated and successfully tested resulting in MOPS using a CMOS fabrication technology This squarer had two additional features increased number of squaring operations per unit circuit area and the potential for reduced power consumption per squaring operation